Three-Dimensional Flash NOR Memory System With Configurable Pins

ABSTRACT

A three-dimensional NOR flash memory system is disclosed. The system optionally comprises configurable standard pins, a configurable output buffer, and a configurable input buffer.

TECHNICAL FIELD

A three-dimensional (3D) NOR flash memory system with configurable pinssuitable for 3D memory system is disclosed.

BACKGROUND OF THE INVENTION

Flash memory cells using a floating gate to store charges thereon andmemory arrays of such non-volatile memory cells formed in asemiconductor substrate are well known in the art. Typically, suchfloating gate memory cells have been of the split gate type, or stackedgate type.

One prior art non-volatile memory cell 10 is shown in FIG. 1. The splitgate SuperFlash (SF) memory cell 10 comprises a semiconductor substrate4 of a first conductivity type, such as P type. The substrate 1 has asurface on which there is formed a first region 2 (also known as thesource line SL) of a second conductivity type, such as N type. A secondregion 3 (also known as the drain line) also of a second conductivitytype, such as N type, is formed on the surface of the substrate 1.Between the first region 2 and the second region 3 is a channel region4. A bit line (BL) 9 is connected to the second region 3. A word line(WL) 8 (also referred to as the select gate) is positioned above a firstportion of the channel region 4 and is insulated therefrom. The wordline 8 has little or no overlap with the second region 3. A floatinggate (FG) 5 is over another portion of the channel region 4. Thefloating gate 5 is insulated therefrom, and is adjacent to the word line8. The floating gate 5 is also adjacent to the first region 2. Acoupling gate (CG) 7 (also known as control gate) is over the floatinggate 5 and is insulated therefrom. An erase gate (EG) 6 is over thefirst region 2 and is adjacent to the floating gate 5 and the couplinggate 7 and is insulated therefrom. The erase gate 6 is also insulatedfrom the first region 2.

One exemplary operation for erase and program of prior art non-volatilememory cell 10 is as follows. The cell 10 is erased, through aFowler-Nordheim tunneling mechanism, by applying a high voltage on theerase gate EG 6 with other terminals equal to zero volt. Electronstunnel from the floating gate FG 5 into the erase gate EG 6 causing thefloating gate FG 5 to be positively charged, turning on the cell 10 in aread condition. The resulting cell erased state is known as ‘1’ state.The cell 10 is programmed, through a source side hot electronprogramming mechanism, by applying a high voltage on the coupling gateCG 7, a high voltage on the source line SL 2, a medium voltage on theerase gate EG 6, and a programming current on the bit line BL 9. Aportion of electrons flowing across the gap between the word line WL 8and the floating gate FG 5 acquire enough energy to inject into thefloating gate FG 5 causing the floating gate FG 5 to be negativelycharged, turning off the cell 10 in read condition. The resulting cellprogrammed state is known as ‘0’ state.

The cell 10 can be inhibited in programming (if, for instance, anothercell in its row is to be programmed but cell 10 is to not be programmed)by applying an inhibit voltage on the bit line BL 9. The cell 10 is moreparticularly described in U.S. Pat. No. 7,868,375, whose disclosure isincorporated herein by reference in its entirety.

Also known in other areas of art are three-dimensional integratedcircuit structures. One approach is to stack two or more separatelypackaged integrated circuit chips and to combine their leads in a mannerthat allows coordinated management of the chips. Another approach is tostack two or more dies within a single package.

However, to date, the prior art has not included three-dimensionalstructures involving flash memory.

SUMMARY OF THE INVENTION

The aforementioned needs are addressed through multiple embodimentsinvolving three-dimensional arrangements of flash memory arrays andassociated circuitry. The embodiments provide efficiencies in physicalspace utilization, manufacturing complexity, power usage, thermalcharacteristics, and cost.

In one embodiment, configurable pins are provided for use with thethree-dimensional flash memory device.

In another embodiment, a configurable output buffer is provided for usewith the three-dimensional flash memory device.

In another embodiment, a configurable output buffer is provided for usewith the three-dimensional flash memory device.

In another embodiment, a configurable input buffer is provided for usewith the three-dimensional flash memory device.

In another embodiment, flash memory device is a serial NOR product typesuch as the SuperFlash Serial SPI SST25VF016B or Serial Quad I/OSST26VF064B or other serial NOR product types. In an embodiment flashmemory device is a SuperFlash parallel NOR product type such as theParallel MPF SST38VF640xB or other parallel NOR product types.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a prior art non-volatile memory cellto which the present invention can be applied.

FIG. 2 depicts a prior art, two-dimensional flash memory system layout.

FIG. 3 depicts a first die within a three-dimensional flash memorysystem embodiment.

FIG. 4 depicts a second die within a three-dimensional flash memorysystem embodiment.

FIG. 5 depicts a first die within another three-dimensional flash memorysystem embodiment.

FIG. 6 depicts a second die within a three-dimensional flash memorysystem embodiment.

FIG. 7. depicts an optional peripheral flash control die that can beused in a three-dimensional flash memory system embodiment.

FIG. 8 depicts an embodiment of supplemental circuitry for use with diescontaining flash memory arrays.

FIG. 9 depicts an embodiment of control circuitry.

FIG. 10 depicts a sensing system that can be used in a three-dimensionalflash memory system embodiment.

FIG. 11 depicts a TSV design that can be used in a three-dimensionalflash memory system embodiment.

FIG. 12 depicts a sensing circuit design that can be used in athree-dimensional flash memory system embodiment.

FIG. 13 depicts a source follower TSV buffer circuit design that can beused in a three-dimensional flash memory system embodiment.

FIG. 14 depicts a high voltage circuit design that can be used in athree-dimensional flash memory system embodiment.

FIG. 15 depicts a flash memory sector architecture that can be used in athree-dimensional flash memory system embodiment.

FIG. 16 depicts an EEPROM emulator memory sector architecture that canbe used in a three-dimensional flash memory system embodiment.

FIG. 17 depicts another embodiment of a three-dimensional flash memorysystem.

FIG. 18 depicts another embodiment of a three-dimensional flash memorysystem.

FIG. 19 depicts another embodiment of a three-dimensional flash memorysystem.

FIG. 20 depicts an embodiment of a high voltage supply within athree-dimensional flash memory system.

FIG. 21 depicts configurable pins used in a three-dimensional flashmemory system.

FIG. 22 depicts a configurable output buffer used in a three-dimensionalflash memory system.

FIG. 23 depicts a configurable output buffer used in a three-dimensionalflash memory system.

FIG. 24 depicts a configurable input buffer used in a three-dimensionalflash memory system

FIG. 25 depicts an output stage of a three-dimensional flash memorysystem.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 depicts a typical prior art architecture for a two-dimensionalprior art flash memory system. Die 12 comprises: memory array 15 andmemory array 20 for storing data, the memory array optionally utilizingmemory cell 10 as in FIG. 1; pad 35 and pad 80 for enabling electricalcommunication between the other components of die 12 and, typically,wire bonds (not shown) that in turn connect to pins (not shown) orpackage bumps that are used to access the integrated circuit fromoutside of the packaged chip; high voltage circuit 75 used to providepositive and negative voltage supplies for the system; control logic 70for providing various control functions, such as redundancy and built-inself-testing; analog logic 65; sensing circuits 60 and 61 used to readdata from memory array 15 and memory array 20, respectively; row decodercircuit 45 and row decoder circuit 46 used to access the row in memoryarray 15 and memory array 20, respectively, to be read from or writtento; column decoder 55 and column decoder 56 used to access the column inmemory array 15 and memory array 20, respectively, to be read from orwritten to; charge pump circuit 50 and charge pump circuit 51, used toprovide increased voltages for read and write operations for memoryarray 15 and memory array 20, respectively; high voltage driver circuit30 shared by memory array 15 and memory array 20 for read and writeoperations; high voltage driver circuit 25 used by memory array 15during read and write operations and high voltage driver circuit 26 usedby memory array 20 during read and write operations; and bitline inhibitvoltage circuit 40 and bitline inhibit voltage circuit 41 used toun-select bitlines that are not intended to be programmed during a writeoperation for memory array 15 and memory array 20, respectively. Thesefunctional blocks are understood by those of ordinary skill in the art,and the block layout shown in FIG. 2 is known in the prior art. Notably,this prior art design is two-dimensional.

FIG. 3 depicts a first die in a three-dimensional flash memory systemembodiment. Die 100 comprises many of the same components previouslyshown in FIG. 2. Structures that are common to two or more figuresdiscussed herein have been given the same last two digits in thecomponent numbering. For example, array 115 in FIG. 3 corresponds toarray 15 in FIG. 2. For efficiency's sake, the description of FIG. 3will focus on components that have not yet been described.

Die 100 comprises TSV (through-silicon via) 185 and TSV 195 and testpadblock TPAD 135. TSVs are known structures in the prior art. A TSV is anelectrical connection that passes through a silicon wafer or die andconnects circuits that reside in different dies or layers within anintegrated circuit package. TSV 185 comprises a plurality of conductors186 a 1 . . . 186 ai. TSV 195 comprises a plurality of conductors 196 a1 . . . 196 ak. Conductors 186 a 1 . . . 186 ai and conductors 196 a 1 .. . 196 ak are surrounded by non-conductive material, such as plasticmolding.

The TSV 185 and 195 are strategically placed away from the flash arrays115 and 120 by a predetermined distance (e.g., 30 μm) to avoidinterference or other problems such as mechanical stress from TSVprocessing that could affect the flash arrays 115 and 120. This TSVplacement strategy is applied for the other embodiments discussed hereinthat utilize TSVs. Conductors 186 a 1 . . . 186 ai and conductors 196 a1 . . . 196 ak typically each has tens of milliohms of resistance and50-120 femto-farads of capacitance.

The testpad block TPAD 135 includes probe pads (e.g., pad openings for atester to electrically access the wafer) and 3D die-interface testcircuits and are used by a tester to test die 100 to see if it is a gooddie. Such testing can include a TSV connectivity test, which involvestesting the TSV prior to 3D stacking. This testing can be performed aspart of a pre-bonding test. The JTAG design for a test standard (JointTest Action Group, also known as IEEE 1149.1 Standard Test Access Portand Boundary-Scan Architecture) test method can be employed through theTPAD 135 for testing. The TSV 185 and 195 (and similarly, other TSVsdescribed in other embodiments) can also be used for testing to identifygood dies from bad dies during manufacturing. In this instance, multipleTSV conductors can be tested at one time by one tool of approximately40-50 μm in size by a tester.

With reference still to FIG. 3, optionally die 115 can be a primarymemory array and die 120 a redundant memory array.

FIG. 4 depicts a second die in the three-dimensional flash memory systemembodiment to be used in conjunction with die 100 shown in FIG. 3. Die200 comprises many of the same components previously shown in FIG. 2.Again, for efficiency's sake, the description of FIG. 4 will focus oncomponents that have not yet been described.

Die 200 comprises TSV 185 and TSV shown previously in FIG. 3, as well asTPAD 235. TSV 185 and TSV 195 enable certain elements in die 100 and die200 to be electrically connected to one another, via conductors 186 a 1. . . 186 ai and conductors 196 a 1 . . . 196 ak. The testpad TPAD 235is used by a tester to test to determine if die 200 is a good die before3D stacking, as described previously for testpad TPAD 135 with referenceto FIG. 3.

Optionally, die 215 can be a primary memory array and die 220 aredundant memory array.

Because die 200 and die 100 are located in close proximity to each otherand can communicate via TSV 185 and TSV 195, die 200 is able to sharecertain circuit blocks with die 100. Specifically, die 200 is configuredto use charge pump circuits 150 and 151, analog circuit 165, controllogic 170, and high voltage circuit 175 within die 100, through TSV 185and TSV 195. Die 200 therefore does not need to contain its own versionsof those blocks. This results in efficiency in terms of physical space,manufacturing complexity, and thermal performance. Optionally, die 100can be considered the “master” flash die and die 200 can be consideredthe “slave” flash die.

FIG. 5 depicts a first die in another embodiment of a three-dimensionalflash memory system, and FIG. 6 depicts a second die in that embodiment.Die 300 shown in FIG. 5 is similar to die 100 shown in FIG. 3, exceptthat die 300 does not have a charge pump circuit or high voltagecircuit. Die 400 shown in FIG. 6 is similar to die 200 shown in FIG. 4except that die 400 does not have a sensing circuit. Die 300 and die 400are coupled via TSV 385 and TSV 386. TSV 385 comprises conductors 386 a1 . . . 386 ai, and TSV 386 comprises conductors 396 a 1 . . . 396 ai.Optionally, die 315 can be a primary memory array and die 320 aredundant memory array, and/or die 415 can be a primary memory array anddie 420 a redundant memory array. Testpads TPAD 335 and 435 are used bya tester to determine if die 300 and die 400 are good dies before 3Dstacking.

FIG. 7 depicts an optional peripheral flash control die for use with anyof the embodiments discussed herein. Die 500 contains circuitry forassisting other dies in performing the functions of a flash memorysystem. Die 500 includes TSV 585, TSV 595 and test pad TPAD 535. TSV 585comprises conductors 586 a 1 . . . 586 ai, and TSV 386 comprisesconductors 596 a 1 . . . 596 ak. Die 500 comprises analog logic 565,control logic 570 and high voltage circuit 545. Die 500 can be used inconjunction with die 200, die 300, and/or die 400 to provide circuitblocks for use with those dies that are not physically present withinthose dies. This is enabled through TSV 585 and TSV 586. One of ordinaryskill in the art will understand that, although numbered differently,TSV 585 and TSV 586 can be the same TSVs described previously withreference to other dies. The testpad TPAD 535 is used by a tester totest die 500 to see if it is a good die before 3D stacking.

FIG. 8 depicts a charge pump die for use with any of the embodimentsdiscussed herein. Die 601 contains charge pump circuitry 602 to generatethe voltages needed for other dies in performing flash memoryerase/program/read operations. Die 601 includes TSV 695. TSV 695comprises conductors 696 a 1 . . . 696 ak. Die 601 can be used inconjunction with other dies through TSV 695. One of ordinary skill inthe art will understand that, although numbered differently, TSV 695 canbe the same TSVs described previously with reference to other dies.Testpad TPAD 635 is used by a tester to determine if die 601 is a gooddie before 3D stacking.

Analog circuits 165, 365, and 565 shown in FIGS. 3, 5, and 7 can providea multitude of functionality within the memory system, including thefollowing: transistor trimming during the manufacturing process,temperature sensing for the trimming process, timers, oscillators, andvoltage supplies.

Sensing circuits 160, 260, and 360 shown in FIGS. 3, 4, and 5 cancomprise numerous components used in the sensing operation, including asense amplifier, transistor trimming circuits (utilizing the trimminginformation generated by the transistor trimming process performed byanalog circuits 165, 365, and/or 565) temperature sensors, referencecircuits, and a reference memory array. Optionally, a die can includefewer than all of these categories of circuits. For example, a die mightinclude only a sense amplifier.

FIG. 9 depicts an optional embodiment for control logic 170, 370, and570, shown as logic block 600. Logic block 600 optionally comprisespowerup recall controller 610, First Die Redundancy Circuit 620, SecondDie Redundancy Circuit 630, Redundancy Controller 640, RedundancyComparator 650, EEPROM Emulator 660, Sector Size M Emulator 670 andSector Size N Emulator 680.

Powerup recall controller 610 manages the startup of the flash memorysystem, including performing the built-in self-test functionality. Italso fetches the configuration data for transistor trimming that wasgenerated during the manufacturing process.

First Die Control Circuit 620 stores a list of memory cells in thearrays located in a first die that are determined during power up oroperation to be faulty or subject to error. First Die Control Circuit620 stores this information in non-volatile memory. First Die ControlCircuit 620 also stored transistor trimming data generated during themanufacturing and testing phase. Upon power up, powerup recallcontroller 610 will retrieve the list of bad memory cells from First DieControl Circuit 620, and Redundancy Controller 640 thereafter will mapthe bad storage cells to addresses for redundant (and good) cells, sothat all accesses to the bad cells will instead be directed to goodcells.

First Die Control Circuit 620 also stores trimming data for a first diethat was generated during the manufacturing or testing process.Transistor trimming techniques to compensate for manufacturingvariability in integrated circuits are known in the art.

First Die Control Circuit 620 also performs built-in self-tests. Onetype of test is disclosed in U.S. application Ser. No. 10/213,243, U.S.Pat. No. 6,788,595, “Embedded Recall Apparatus and Method in NonvolatileMemory” (the “'595 patent”) assigned to a common assignee, which ishereby incorporated by reference. The '595 patent discloses the storageof a pattern of predetermined bits in a memory array and in a register.During the startup process, the bits from the memory array are comparedto the bits in the register. This process is repeated until a set numberof “passes” or “failures” occurs. The purpose of this test is tovalidate different portions of the memory array. If any failures areidentified, then the relevant cells can be added to the list of “bad”cells.

Second Die Control Circuit 630 performs the same function as First DieRedundancy Circuit 620 but for a second die. One of ordinary skill inthe art will understand that a Control Circuit such as First Die ControlCircuit 620 and Second Die Control Circuit 630 can be used for eachadditional die in the memory system.

Redundancy controller 640, already discussed above, maps bad storagecells to addresses for good storage cells, so that the bad storage cellsare no longer used during normal operation. Redundancy comparator 640compares in real time incoming address versus bad addresses stored todetermine if addressed storage cells needs to be replaced. Optionally,redundancy controller 640 and redundancy comparator 650 can be shared bymore than one die.

EE Emulator Controller 660 enables the memory system to emulate anEEPROM. For example, EEPROMs typically utilize memory of a certainsector size of a small number of bytes, such as 8 bytes (or 16, 32, 64bytes) per sector. A physical flash memory array will contain thousandsof rows and columns. EE Emulator controller 660 can divide an array intogroups of 8 or 64 bytes (or whatever the desired sector size is) and canassign sector numbers to each set of 8 or 64 bytes. Thereafter, EEemulator controller 660 can receive commands intended for an EEPROM andcan perform read or write operations to the flash array by translatingthe EEPROM sector identifiers into row and column numbers that can beused with an array within a die. In this manner, the system emulates theoperation of an EEPROM.

Sector Size N Controller 670 enables the memory system to operate onsectors of size N bytes. Sector Size N Controller 660 can divide anarray into sets of N bytes and can assign sector numbers to each set ofN bytes. Thereafter, Sector Size N Controller 670 can receive commandsintended for one or more sectors of size N bytes, and the system canperform read or write operations accordingly by translating the sectoridentifiers into row and column numbers that can be used with an arraywithin a die.

Sector Size M Controller 680 enables the memory system to operate onsectors of size M bytes. Sector Size M Controller 680 can divide anarray into sets of M bytes and can assign sector numbers to each set ofM bytes. Thereafter, Sector Size M Controller 680 can receive commandsintended for one or more sectors of size M bytes, and the system canperform read or write operations accordingly by translating the sectoridentifiers into row and column numbers that can be used with an arraywithin a die.

One of ordinary skill in the art will appreciate that numerous sectorsize controllers can be utilized to emulate sectors of various sizes.

One advantage of the disclosed embodiments is the ability to handle readand write requests to sectors of different sizes. For example, one arraycan be dedicated to handling read and write requests to sectors with asize of 2K bytes per sector, and another array can be dedicated tohandling read and write requests to sectors with a size of 4K bytes persector. This will allow a single flash memory system to emulate multipletypes of legacy memory systems, such as RAM, ROM, EEROM, EEPROM, EPROM,hard disk drives, and other devices.

Another advantage of the disclosed embodiments is that different diescan be fabricated using different processes. For example, die 100 can befabricated using a first semiconductor process, such as 40 nm, and die200 can be fabricated using a second semiconductor process, such as 65nm. Because die 500 does not contain any memory arrays, it optionallycan be fabricated using a semiconductor process optimized for analoglogic, such as 130 nm.

FIG. 10 depicts a sensing system 1100 that can be used in thethree-dimensional flash memory system embodiments described herein. Thesensing system 1100 comprises SF (SuperFlash split gate technology, suchas the memory cell as described in FIG. 1) Embedded Reference Array1110, Reference Readout Circuit 1120, Read Margin Trim Circuit 1130,Temperature Sensor 1140, Sense Amplifier 1150, and Sense Amplifier 1160.In one embodiment, Sense Amplifier 1160 is implemented on die 200 and300, and the rest of circuit blocks shown in FIG. 10 are implemented ondie 100.

The SF Embedded Reference Array 1110 provides the reference cell neededto generate reference levels to be compared against the data level(generated from a data memory cell). The reference level is generated bythe Reference Readout Circuit 1120. The comparison is done by the SenseAmplifier 1150, and its output signal is DOUT 1152. The Read Margin TrimCircuit 1130 is used to adjust the reference level to different levelsneeded to ensure data memory cell integrity against PVT (process,voltage, and temperature) variations and stress conditions. TheTemperature Sensor 1140 is needed to compensate for temperature gradientfor different dies in the vertical die stacking in the three-dimensionalflash memory system. Because the circuit blocks 1110, 1120, 1130, 1140are manufactured on one master die (e.g., die 100), less overhead andpower is needed for the three-dimensional flash memory operation. Thissensing architecture saves power and area without sacrificingperformance.

FIG. 11 depicts a TSV shield design 1200 for critical signals tominimize noise impact. The 1200 TSV shield design includes TSV 1296 afor critical signals such for routing read signal paths such as forsignal 1122 IREF and signal 1152 DOUTx in FIG. 10 or for signals such asfor output of the sensing 160 in FIG. 4 or the signal of block 455 inFIG. 6. Other critical signals include address lines, clocks, andcontrol signals. The TSV 1296 b serves as shielding signal lines for theTSV 1296 a to minimize cross talk from other signals to the TSV 1296 aas well as prevent noise projected from the TSV 1296 a to other TSV.

FIG. 12 depicts a sensing circuit 1250 that can be used in thethree-dimensional flash memory system embodiment. The sensing circuit1250 includes load (pullup) PMOS transistor 1252, a cascoding nativeNMOS transistor 1254 (with a threshold voltage ˜0V), a bitline bias NMOStransistor 1256, and a bitline bias current source 1260. Alternativelythe load PMOS transistor 1252 can be replaced with a current source, anative NMOS transistor, or a resistor. Alternatively instead of thecurrent source 1260 and the NMOS transistor 1256, a bias voltage on thegate of the NMOS transistor 1254 can be used to determine the biasvoltage on the bit line BLIO 1258. Bit line BLIO 1258 (source of NMOS1254) couples to a memory cells through a y-decoder and a memory array(similar to ymux 255 and array 215 in FIG. 4, for example). A sensednode SOUT 1262 couples to a differential amplifier 1266. A referenceSREF 1264 couples to another terminal of the differential amplifier1266. A senseamp output SAOUT 1268 is output of differential amplifier1266. As partitioned, the sensing circuit 1250 is used to drive a TSVparasitic capacitor 1259 (which comes from a TSV used to connect a dieto next die in the 3D stack) through the cascoding transistor 1254. Sucharrangement minimizes the sensing speed penalty since the sensed nodeSOUT 1262 does not see the TSV parasitic capacitor 1259 directly.

FIG. 13 depicts a source follower TSV buffer circuit 1350 that can beused in the three-dimensional flash memory system embodiments. Thesource follower TSV buffer 1350 is used to drive a TSV connection. TheTSV buffer includes a native (threshold voltage ˜0V) NMOS transistor1352 and a current source 1354. The circuit 1350 is used in oneembodiment at the output of the sensing circuit 260 (FIG. 3), thesensing circuit 360 (FIG. 4), the ymux circuit 455 (FIG. 6) to drive aTSV across the die stack. The circuit 1350 can also be used for otheranalog signals such as bandgap reference voltage.

FIG. 14 depicts an analog high voltage (HV) system 1300 that can be usedin the three-dimensional flash memory system embodiment. The analog HVsystem 1300 includes a bandgap reference block 1310, a timer block 1320,a high voltage generation HVGEN 1330, a HV trimming HV TRIM 1340, and atemperate sensing block TEMPSEN 1350. The TEMPSEN 1350 is used tocompensate the temperature gradient of the 3D die stack by adjusting thehigh voltage depending on each die temperature. The HV TRIM 1340 is usedto trim the high voltage levels to compensate the process variation ofeach die in the stack.

The analog HV system 1300 also includes analog HV level wordline driver1360 a-d for VWLRD/VWLP/VWLE/VWLSTS (wordlineread/program,/erase/stress) respectively. The analog HV system 1300 alsoincludes analog HV level control gate driver 1365 a-d forVCGRD/VCGP/VCGE/VCGSTS (control gate read/program,/erase/stress)respectively. The analog HV system 1300 also includes analog HV levelerase gate driver 1370 a-d for VEGRD/VEGP/VEGE/VEGSTS (erase gateread/program,/erase/stress) respectively. The analog HV system 1300 alsoincludes analog HV level source line driver 1375 a-d forVSLRD/VSLP/VSLE/VSLSTS (source line read/program,/erase/stress)respectively. The analog HV system 1300 also includes analog HV leveldriver 1390 for muxing the input level VINRD/VINP/VINE/VINSTS (inputline read/program,/erase/stress) respectively. The analog HV system 1300also includes analog HV level driver 1380 for muxing the input levelVSLRD/VSLP/VSLE/VSLSTS (input line read/program,/erase/stress)respectively to input of a source line supply circuit 1385 VSLSUP.

In one embodiment, circuit blocks 1310-1350 are implemented on a masterSF die 100 (FIG. 3) or on a peripheral flash control die 500 (FIG. 7).In another embodiment, circuit blocks 1360 a-d/1365 a-d/1370 a-d/1375a-d are implemented on a master flash die such as die 100 (FIG. 3) or ona peripheral flash control die 500 (FIG. 7). In another embodiment,circuit blocks 1380/1385/1390 are implemented on a slave flash die suchas die 300 (FIG. 5).

FIG. 15 depicts an flash memory sector architecture 1400 that can beused in the three-dimensional flash memory system embodiment. The sectorarchitecture 1400 includes multiple memory cells 1410 that is arrangedinto bitlines (columns) and rows. The memory cell 1410 is as the memorycell 10 in FIG. 1. The sector architecture includes a flash sector 1420that includes 8 wordlines WL0-7 1430-1437, 2K bitlines 0-2047 1470-1 to1470-N, one CG line 1440 a (connecting all CG terminal of all memorycells 1410 in sector 1420), one SL line 1460 a (connecting all SLterminal of all memory cells 1410 in sector 1420), one EG line 1450 a(connecting all EG terminal of all memory cells 1410 in sector 1420). Assuch there are 2K bytes of memory cells 1410 in the sector 1420.Different number of bytes per sector can be implemented by using more orless number of wordline and more or less number of bitlines such as 8wordlines and 4K bitlines (4K bytes per sector). Multiple of sector 1420can be arranged horizontally with all wordlines shared horizontallyacross. Multiples of sectors 1420 can be tiled vertically to increasethe array density with all bitlines shared vertically.

FIG. 16 depicts an EE emulator sector architecture 1500 that can be usedin the three-dimensional flash memory system embodiment. The sectorarchitecture 1400 includes multiple memory cells 1510 that is arrangedinto bitlines (columns) and rows. The memory cell 1510 is as the memorycell 10 in FIG. 1. The EE emulator sector architecture includes a flashEE emulator sector 1515 that includes 2 wordlines WL0-1 1530-1531, 256bitlines 0-255 1570-1 to 1570-N, one CG line 1540 a (connecting all CGterminal of all memory cells 1410 in sector 1515), one SL line 1560 a(connecting all SL terminal of all memory cells 1410 in sector 1515),one EG line 1550 a (connecting all EG terminal of all memory cells 1510in sector 1420). As such there are 64 bytes of memory cells 1510 in theEE emulator sector 1515. Smaller number of bytes per EE emulator sectorcan be implemented by using less number of wordline and less number ofbitlines, such as 1 wordline and 64 bitlines (8 bytes per EE emulatorsector). The flash EE emulator sector 1515 is tiled vertically to makeup a plane array 1520 with all bitlines shared vertically. The planearray 1520 is tiled horizontally to make multiples of it will allwordlines are shared horizontally.

Another embodiment is shown in FIG. 17. Integrated circuit 700 comprisesa plurality of dies. In this example, integrated circuit 700 comprisesdie 710, die 720, die 730, die 740, and die 750. Die 710 is mounted onsubstrate 760 using flipchip connections 780. The substrate 760 connectsto package bumps 790, which can be used by devices outside of integratedcircuit 700 to access integrated circuit 700. TSV 785 connects differentdies together. A first subset of TSV 785 connects die 710, die 720, die740, and die 750 together, and a second subset of TSV 785 connects due710, die 720, and die 730 together. Within TSV 785 are microbumps 770used to connect to dies. Die 730 and die 740 are located within the same“level” or dimension within integrated circuit 700.

In one example based on this embodiment, the die 710 is a MCU(microcontroller) die, CPU (Central Processing Unit) die, or a GPU(Graphics Processing Unit) die, die 720 is a master flash die, die 740is a slave flash die, die 750 is a RAM die, and die 730 is peripheralflash control die or a charge pump die.

Another advantage of the disclosed embodiments is that different diescan be fabricated using different processes. For example, die 710 can befabricated using a first semiconductor process, such as 14 nm, and die720/740 can be fabricated using a second semiconductor process, such as40 nm. Because die 730 does not contain any memory arrays, it optionallycan be fabricated using a semiconductor process optimized for analoglogic, such as 65 nm.

Another embodiment is shown in FIG. 18. Integrated circuit 800 comprisesa plurality of dies. In this example, integrated circuit 800 comprisesdie 810, die 820, die 830, die 840, and die 850. Die 850 is mounted onsubstrate 860 using flipchip connections 880. The substrate 860 connectsto package bumps 890, which can be used by devices outside of integratedcircuit 800 to access integrated circuit 800. A subset of TSV 885connects die 810, die 830, die 840, and die 850 together, and a secondsubset of TSV 885 connects die 810 and die 820 together. Within TSV 885are microbumps 870 used to connect to dies.

In one example based on this embodiment, die 810 is a master flash die,die 830/840/850 are slave flash dies, and die 820 is peripheral flashcontrol die or a charge pump die.

Another embodiment is shown in FIG. 19. Integrated circuit 900 comprisesa plurality of dies. In this example, integrated circuit 900 comprisesdie 910, die 920, die 930, die 940, die 950, and die 960. Die 910 and950 are mounted on substrate 970 using flipchip connections 990. The die910 and 950 are connected together through a silicon interposer 980. Thesubstrate 970 connects to package bumps 995, which can be used bydevices outside of integrated circuit 900 to access integrated circuit900. A first subset of TSV 985 connects die 910, die 920, die 930, anddie 940 together, and a second subset of TSV 985 connects die 950 anddie 960 together. Within TSV 985 are microbumps 970 to connect to dies.

In one exampled based on this embodiment, he die 910 is a master flashdie, die 920/930/940 are slave flash dies, and die 950/960 areperipheral flash control dies.

An embodiment of a force-sense high voltage supply is shown in FIG. 20.Integrated circuit 1000 comprises a plurality of dies. In this example,integrated circuit 1000 comprises die 1010, die 1020, through die 1030(with any number of dies contained between die 1020 and die 1030) (withother optional dies not shown between die 1020 and die 1030). Die 1010contains high voltage supply 1011 which delivers (forces) the highvoltage output to the die 1010, 1020, or 1030. TSV 1085 connects die1010, die 1020, and die 1030. High voltage supply 1011 connects to die1020 and die 1030 through TSV 1085. Device 1021, which optionally cancomprise a switch, is used to control the provision of power from highvoltage supply 1011 to die 1020 by enabling the high voltage output atthe die 1020 to be fed back to the input of the high voltage supply 1011on the die 1010 (meaning the high voltage 1011 senses the voltage on thehigh voltage out on the die 1020 through the switch 1021 so as todeliver the correct voltage at the die 1020).

Similarly, high voltage supply 1011 connects to die 1030 through TSV1085. Device 1031, which optionally can comprise a switch, is used tocontrol the provision of power from high voltage supply 1011 to die 1030by enabling the high voltage output at the die 1030 to be fed back tothe input of the high voltage supply 1011 on the die 1010 (meaning thehigh voltage 1011 senses the voltage on the high voltage out on the die1030 through the switch 1031 so as to deliver the correct voltage at thedie 1030).

The high voltage supply 1011 can be used, for example, as power forsupply terminal SL 2 of memory cell 10 shown in FIG. 1 and used inarrays 115/120/215/220/315/330/415/420. Alternatively, it can supplypower for all terminals WL 8, CG 7, EG 6, BL 9, SL 2, and substrate 1 ofthe memory cell 10 in FIG. 1 and used in memory arrays115/120/215/220/315/330/415/420.

One embodiment containing integrated circuits 700, 800, and/or 900 ismethod of concurrent operation. For example, the control circuit onmaster die 720/810/910 can enable the concurrent operation of differentflash dies, such as die 720 reading/programming/erasing while otherflash die 740 is programming/reading/programming, respectively, orvice-versa.

Another embodiment containing integrated circuits 700, 800, and/or 900is a method of IO width configuration, where the system determines howmany IO bits can be supplied by a die in a read or program operation.For example, the control circuit on master die 720/810/910 can changethe width of IO in a read or program operation of different flash dies,such as by expanding the IO width by combining IO widths of individualdies.

Another embodiment containing integrated circuits 700, 800, and/or 900is method of adaptive temperature sensor configuration. For example, atemperature profile can be stored for each flash die to compensate forthe temperature gradient for the die stack for specific operation sincedifferent systems result in different power consumptions, hence causingdifferent temperature gradient.

Another embodiment containing integrated circuits 700, 800, and/or 900is a method of TSV self test. For example, at initial configuration, abuilt in TSV self test connectivity engine is used to identify adefective TSV and to determine whether it needs repair by using aRedundant TSV or should be discarded. The self test can involve forcinga voltage on a TSV connection and deciding if the TSV is bad, such as bydetermining if the resulting current is smaller than a predeterminednumber. The self test also can involve forcing a current through a TSVconnection and concluding that the TSV is bad if the resulting voltageis greater than a predetermined number.

A method of manufacturing a 3D flash memory device, such as one based onthe embodiments described herein, will now be described. The 3D flashprocess formation starts with individual die process. Thereafter, diesare stacked either using die-to-wafer or wafer-to-wafer stackingschemes.

For die-to-wafer stacking, each die can be tested using KGD (Known GoodDie) method to eliminate bad dies. The TSV processing can be done by VIAfirst (before CMOS), VIA Middle (after CMOS and before BEOLback-end-of-line), or VIA Last (after BEOL) testing. TSV formation isprocessed by a via etching step, which creates an (TSV) opening on thewafer. A thin liner (e.g. silicon dioxide 1000 A) is then formed on theside of the opening. Then a metallization step (e.g., Tungsten or Cu) isformed to fill the hole. A dielectric glue layer (e.g. 1 u thick) isdeposited on top of the die after BEOL. TSV back end processing includesthinning, backside metal formation, micro bump, passivation, dicing.

Die-to-wafer stacking uses a temporary adhesive bonding. Each top waferis typically thinned down to 40-75 um depending on aspect ratio and TSVdiameter, for example for TSV diameter of Sum and aspect ratio of 10, a50 um thick wafer is required. The top diced dies are stacked face up ona regular thickness bottom die through micro-bump and the whole diestack then attaches to a package substrate through flipchip bump(C4-bump).

For wafer-to-wafer bonding, the dies must have a common size, and hence,offers less flexibility in 3D die integration. The TSV process and waferstacking process are similar as described above. The 3D stack yield inthis case would be limited by the lowest yield wafer. Wafer-to-waferstacking typically can use global wafer alignment for bonding, andhence, has higher alignment tolerance and also higher throughput (sinceall die stacking occurs in parallel).

FIG. 21 depicts configurable pins of memory device 1660 that can beimplemented in the 3D memory system as described above. The memorydevice 1660 is a version of the SuperFlash Serial SPI, SuperFlash SerialSQI, SuperFlash Parallel MTP, or SuperFlash Parallel MPF device. Thesedevices are accessed by a standard NOR memory pin interface such asJEDEC standard pin assignment and memory interface. The standardparallel NOR interface pins include CE# (Chip Enable), OE# (OutputEnable), WE# (Write Enable), WP# (Write Protect), RST# (Reset), RY/BY#(Ready Busy), DQ15-DQ0 (Data Input Output, IO pads), AN-A0 (AddressPins), VDD (Power Supply), VSS (Ground). The standard serial SPIinterface pins include SCK (Serial Clock), SI (Serial Data Input), SO(Serial Data Output), CE# (Chip Enable), WR# (Write Protect), HOLD#(Hold), VDD (Power Supply), VDD (Ground). The standard serial SQIinterface pins include SCK (Serial Clock), SI (Serial Data Input),SIO[3:0] (Serial Data Quad Input Output), CE# (Chip Enable), WR# (WriteProtect), HOLD# (Hold), VDD (Power Supply), VDD (Ground).

A set of pins 1625 and control pin 1626 are accessible outside of thepackage of memory device 1660. The set of pins 1625 is coupled to logiccircuit 1628 through interface 1627. Interface 1627 optionally comprisespads and wire bonds as known in the prior art or can comprise TSVs asdescribed previously. Logic circuit 1628 comprises control block 1620.Control block 1620 is coupled to control pin 1626 and controller 1640.Control pin 1626 and controller 1640 each can configure logic circuit1628 to determine the function of the set of pins 1625. Memory device1660 further comprises memory array 1650. Memory array 1650 can beeither a two dimensional memory array or a three dimensional memoryarray.

In one embodiment, memory array 1650 is a two dimensional memory array.If control pin 1626 or the output of controller 1640 is set to “0,” theset of pins 1625 can be configured by logic circuit 1628 to operate as aserial interface to the memory device. If control pin 1626 or the outputof controller 1640 is set to “1,” the set of pins 1625 can be configuredby logic circuit 1628 to operate as a parallel interface to the memorydevice.

In another embodiment, memory array 1650 is a two dimensional memoryarray. If control pin 1626 or the output of controller 1640 is set to“0,” the set of pins 1625 could be configured by logic circuit 1628 toperform the function of normal I/O pins that can access memory array1650. However, if control pin 1626 or the output of controller 1640 isset to “1,” the set of pins 1625 can be configured by logic circuit 1628to perform the function of providing access to internal signals 1645 ofthe memory device, such as internal address signals, internal I/O data,internal control signals, internal current bias signals, testmodecontrol signals, SuperFlash control signals, etc. Such signals were notaccessible to pins in the prior art.

In another embodiment, memory array 1650 is a two dimensional memoryarray. If control pin 1626 or the output of controller 1640 is set to“0,” the set of pins 1625 could be configured by logic circuit 1628 toperform the function of normal I/O pins that can access memory array1650. However, if control pin 1626 or the output of controller 1640 isset to “1,” the set of pins 1625 can be used for testing purposes.

In another embodiment, the set of pins 1625 is configured to be accessedas non-standard NOR memory pins.

In another embodiment, the set of pins 1625 is configured to be a mix ofserial and parallel NOR memory interface. One embodiment of a mixedserial and parallel NOR memory interface is one with serial inputcommand and parallel output read.

In another embodiment, memory array 1650 is a three-dimensional memoryarray. If control pin 1636 or the output of controller 1640 is set to“0,” the set of pins 1625 could be configured by logic circuit 1628 toperform the function of I/O pins for memory array 1650. However, ifcontrol pin 1636 or the output of controller 1640 is set to “1,” the setof pins 1625 can be configured by logic circuit 1628 to perform thefunction of providing access to internal signals 1645 of the memorydevice, such as internal address signals, internal I/O data, internalcontrol signals, internal current bias signals, testmode controlsignals, SuperFlash control signals, etc.

In another embodiment, memory array 1650 is a three dimensional memoryarray. If control pin 1626 or the output of controller 1640 is set to“0,” the set of pins 1625 can be configured by logic circuit 1628 tooperate as a serial interface to memory array 1650. If control pin 1626or the output of controller 1640 is set to “1,” the set of pins 1625 canbe configured by logic circuit 1628 to operate as a parallel interfaceto memory array 1650.

FIG. 22 depicts a configurable output buffer 1700. The configurableoutput buffer 1700 is part of an output circuit of the DQ parallel pinor SO or SIO serial pin. The output buffer is typically specified todrive an output load of 30 pF or 100 pF for a standard NOR memorydevice. Configurable output buffer 1700 comprises predriver 1710 coupledto slew rate controller 1720 and predriver 1711 coupled to slew ratecontroller 1721. Slew rate controller 1720 is coupled to the gate ofPMOS transistor 1730, and slew rate controller is coupled to the gate ofNMOS transistor 1731. Transistor 1730 and transistor 1731 together forman output driver 1760 that provides output 1740. Slew rate controller1720 and slew rate controller 1731 together control the slew rate ofoutput driver 1760. Output driver 1760 is coupled to voltage source1750. The voltage source 1750 can be connected to a different voltagesource for the 3D memory system which is non-standard (i.e., differentthan voltage source for the standard NOR memory device). Transistor 1730and transistor 1731 optionally are trimmable through known techniques.Slew rate controller 1720 and slew rate controller 1721 themselves areconfigurable by controller 1140 (not shown). Thus, transistor 1730 andtransistor 1731 can be configured to optimize performance for a twodimensional or three dimensional memory device. Further the transistors1730 and 1731 together with the slew rate controller 1720 and 1721 canbe configured to optimize performance for a two dimensional or threedimensional memory device such as driving a lesser output load, e.g.,0.2-2 pF, as compared to an output load of a standard NOR memory device,e.g. 30-100 pF. Furthermore, with a very small output load, slew ratecontroller 1720 and 1721 can be disabled, i.e., no slew rate control isneeded.

FIG. 23 depicts a deconfigurable output buffer 1800. The deconfigurableoutput buffer 1800 is part of an output circuit of the DQ parallel pinor SO or SIO serial pin. Deconfigureable output buffer 1800 comprisespredriver 1810 coupled to slew rate controller 1820 and predriver 1811coupled to slew rate controller 1821. Slew rate controller 1820 iscoupled to the gate of PMOS transistor 1830, and slew rate controller is1821 is coupled to the gate of NMOS transistor 1831. Transistor 1830 andtransistor 1831 together form an output driver 1860. The output ofoutput driver 1860 is provided to multiplexer 1850, which is controlledby control signal 1851. Another input to multiplexer 1850 is the outputof predriver 1810. Slew rate controller 1820 and slew rate controller1821 together control the slew rate of output driver 1860. Transistor1830 and transistor 1831 optionally are trimmable through knowntechniques. Slew rate controller 1820 and slew rate controller 1821themselves are configurable by controller 1140 (not shown). Thus,transistor 1830 and transistor 1831 can be configured to optimizeperformance for a two dimensional or three dimensional memory devicesuch as for driving a much smaller output load (e.g., 0.2-2 pF) insteadof 30-100 pF for a standard NOR memory device. In addition, slew ratecontroller 1820 is enabled by enable signal 1822, and slew ratecontroller 1822 is enabled by enable signal 1823. Optionally, enablesignal 1822 can turn off slew rate controller 1820, and enable signal1823 can turn off slew rate controller 1821. In such a situation,control signal 1851 can control multiplexer 1850 to output the signalreceived from predriver 1810. This effectively will cause the input topredriver 1810 to bypass output driver 1860. This is particularlydesirable if standard memory product ESD protection is not required(such as JEDEC ESD standard, e.g. 2 KV HBM or 200V MM), as output driver1860 also serves as ESD protection. ESD protection device incurs acapacitance output load. In another embodiment a smaller non-standardESD structure is configured for a 3D system. Bypassing output driver1860 will increase the speed of the system.

FIG. 24 depicts configurable input buffer 1900. In one embodiment, theinput buffer 1800 is part of an input circuit of the control pin (suchas CE#, WE#, etc), the address pins (AN-A0), the DQ parallel pin or SIor SIO serial pin. Input buffer 1900 comprises predriver 1904 coupled topredriver 1905, which are powered by voltage source 1906, coupled toswitch 1908 controlled by control signal 1912. Input buffer 1900 furthercomprises switch 1907 controlled by control signal 1913. The input topredriver 1904 is input 1901, and the input to switch 1907 is input1902. In this embodiment, input 1901 is an input to a standard pin andinput 1902 is an input to a TSV of the type described previously. Switch1908 and 1907 are coupled to the gate of transistor 1909 and the gate oftransistor 1910. Transistor 1909 and transistor 1910 together form inputdriver 1920. The output of input driver 1920 is input signal 1911. Ifinput 1901 is active, switch 1908 is enabled and switch 1907 isdisabled. Input 1901 will flow through input driver 1920. If input 1902is active, switch 1908 is disabled and switch 1907 is enabled. Input1902 bypasses predriver 1904 and predriver 1905, which results in afaster system. Input 1902 requires less conditioning than input 1901because the three dimensional system described herein operates at thesame operating voltage as the core of the memory system. The input andoutput signals from the memory array therefore do not require driving aload as in the prior art two dimensional systems.

FIG. 25 depicts an output configuration of a memory system 2000 thatcomprises standard pins and 3D memory system pins (such as TSVs,microbump, bondwire, etc) of the type described previously. Memorysystem 2000 comprises sense amplifiers 2010, buffers 2020, datamultiplexers 2030, pads 2040, and pads 2050. In this example, pads 2040and pads 2050 can be connected to any type of output pin known in theart, such as bumps and balls.

If data is being read from a two dimensional array, the data is sensedby sense amplifier 2010, provided to buffers 2020 and multiplexers 2030and finally to pads 2040. However, if data is being read from a threedimensional array, the data is sensed by sense amplifier 2010, providedto buffers 2020, and then provided straight to pads 2050. This resultsin a faster system and takes advantage of the fact that data read from athree dimensional array does not require driving as in the prior art twodimensional arrays. Further the number of the input-output drivers(meaning I/O data bandwidth) such as of a standard NOR memory device isa typical 16 for standard parallel NOR memory device and one or 4 for astandard serial NOR memory device, hence available I/O data bandwidthfor a standard NOR memory device is depending on this fixed number ofinput-output I/O drivers. For the 3D memory system, the memory system2000 can be configured to provide more than the fixed number of standardNOR memory device. As the embodiment shown in the memory system 2000, 64input-output I/O drivers are provided. This enhances the I/O databandwidth of the 3D memory system. Another embodiment can provide morethan 64 input-output I/O data bandwidth such as 128 to 2K at the expenseof the complexity of the memory system 2000.

2D or 2.5D or other 3D flash memory system such as Multi-Chip-Module,SiP System-In-Package, PoP Package-on-package, and Multi Chip Packagingusing a combination of bond-wire, flip chip, soldier ball and other diebonding and die connecting techniques are applicable to the describedherein inventions.

References to the present invention herein are not intended to limit thescope of any claim or claim term, but instead merely make reference toone or more features that may be covered by one or more of the claims.Materials, processes and numerical examples described above areexemplary only, and should not be deemed to limit the claims. It shouldbe noted that, as used herein, the terms “over” and “on” bothinclusively include “directly on” (no intermediate materials, elementsor space disposed there between) and “indirectly on” (intermediatematerials, elements or space disposed there between). Likewise, the term“adjacent” includes “directly adjacent” (no intermediate materials,elements or space disposed there between) and “indirectly adjacent”(intermediate materials, elements or space disposed there between). Forexample, forming an element “over a substrate” can include forming theelement directly on the substrate with no intermediatematerials/elements there between, as well as forming the elementindirectly on the substrate with one or more intermediatematerials/elements there between. The invention described herein appliesto other non-volatile memory, such as stacked floating gate, ReRAM(Resistive RAM), MRAM (magnoresistive random access memory), FeRAM(Ferroelectric RAM), ROM, and other known memory devices.

What is claimed is:
 1. A three-dimensional memory system, comprising: a plurality of standard pins coupled to a logic circuit; the logic circuit comprising a control block; a memory array; the plurality of pins configurable by the control block to perform a function chosen from a plurality of functions, wherein one of the plurality of functions is accessing the array.
 2. The system of claim 1, wherein one of the functions is providing a standard serial memory interface to the array.
 3. The system of claim 1, wherein one of the functions is providing a non-standard serial memory interface to the array.
 4. The system of claim 1, wherein one of the functions is providing a standard parallel interface to the array.
 5. The system of claim 1, wherein one of the functions is providing a non-standard parallel interface to the array.
 6. The system of claim 1, wherein one of the functions is providing a miled serial and parallel interface to the array.
 7. The system of claim 1, wherein one of the functions is providing a testing function.
 8. The system of claim 1, wherein one of the functions is providing access to internal signals of the memory system.
 9. The system of claim 1, wherein the control block is controlled by a control pin.
 10. The system of claim 1, wherein the control block is controlled by a controller.
 11. The system of claim 1, wherein at least one pin is coupled to the logic circuit through a TSV.
 12. The system of claim 1, wherein at least one pin is coupled to the logic circuit through a microbump.
 13. The system of claim 1, wherein at least one pin is coupled to the logic circuit through a bondwire.
 14. The system of claim 1, wherein the array is a SuperFlash array.
 15. The system of claim 1, wherein the standard pin is a serial SPI or SQI pin.
 16. The system of claim 1, wherein the standard pin is a parallel MPF pin.
 17. The system of claim 1, wherein the interface pin is deconfigured without ESD or with a smaller ESD structure.
 18. The system of claim 1, wherein the output pin is configured optimizing for 3D smaller load performance.
 19. The system of claim 1, wherein the input pin is configured optimizing for 3D performance.
 20. The system of claim 1 further comprising data bandwidth that is more than the standard NOR memory I/O bandwidth.
 21. The system of claim 1 further comprising a microcontroller.
 22. A three-dimensional memory system, comprising: a plurality of pins coupled to a logic circuit; the logic circuit comprising a control block; a memory array; and the plurality of pins configurable by the control block to perform a first function or a second function, wherein the first function is providing addresses to the memory array and the second function is accessing internal signals of the memory system.
 23. The system of claim 22, wherein the internal signals comprise internal address signals.
 24. The system of claim 22, wherein the internal signals comprise internal input-output signals.
 25. The system of claim 22, wherein the internal signals comprise internal control signals.
 26. The system of claim 22, wherein the control block is controlled by a control pin.
 27. The system of claim 22, wherein the control block is controlled by a controller.
 28. The system of claim 22, wherein at least one pin is coupled to the logic circuit through a TSV.
 29. The system of claim 22, wherein the array is a SuperFlash array.
 30. The system of claim 22, wherein the standard pin is a serial SPI or SQI pin.
 31. The system of claim 22, wherein the standard pin is a parallel MPF pin.
 32. The system of claim 22, wherein the interface pin is deconfigured without ESD or with a smaller ESD structure.
 33. The system of claim 22, wherein the output pin is configured optimizing for 3D smaller load performance.
 34. The system of claim 22, wherein the input pin is configured optimizing for 3D performance.
 35. The system of claim 22 further comprising I/O data bandwidth that is more than the standard NOR memory I/O bandwidth.
 36. The system of claim 22 further comprising a microcontroller.
 37. A memory system, comprising: a plurality of pins coupled to a logic circuit; the logic circuit comprising a control block; and a memory array; wherein the plurality of pins are configurable by the control block to perform a first function or a second function, wherein the first function is providing a serial interface to the memory array and the second function is providing a parallel interface to the memory array.
 38. The system of claim 37, wherein the memory array is a two dimensional memory array.
 39. The system of claim 37, wherein the memory array is a three dimensional memory array.
 40. The system of claim 37, wherein the serial interface is a standard interface.
 41. The system of claim 37, wherein the serial interface is a non-standard interface.
 42. The system of claim 37, wherein the parallel interface is a standard interface.
 43. The system of claim 37, wherein the parallel interface is a non-standard interface.
 44. The system of claim 38, wherein the control block is controlled by a control pin.
 45. The system of claim 38, wherein the control block is controlled by a controller.
 46. The system of claim 37, wherein at least one pin is coupled to the logic circuit through a TSV.
 47. The system of claim 37, wherein the array is a SuperFlash array.
 48. The system of claim 37, wherein the standard pin is a serial SPI or SQI pin.
 49. The system of claim 37, wherein the standard pin is a parallel MPF pin.
 50. The system of claim 37, wherein the interface pin is configured without standard ESD or with a smaller non-standard ESD structure.
 51. The system of claim 37, wherein the output pin is configured optimizing for smaller non-standard load performance.
 52. The system of claim 37, wherein the input pin is configured optimizing for non-standard NOR memory interface performance.
 53. The system of claim 37 further comprising I/O data bandwidth that is more than the standard NOR memory I/O bandwidth.
 54. The memory system of claim 37 further comprising a microcontroller.
 55. A three-dimensional memory system, comprising: a plurality of standard memory pins coupled to a logic circuit; a memory array; the plurality of pins configurable to perform a function chosen from a plurality of functions, wherein one of the plurality of functions is accessing the array.
 56. The system of claim 55, wherein one of the functions is providing a standard serial memory interface to the array.
 57. The system of claim 55 wherein one of the functions is providing a non-standard serial memory interface to the array.
 58. The system of claim 55, wherein one of the functions is providing a standard parallel memory interface to the array.
 59. The system of claim 55, wherein one of the functions is providing a non-standard parallel memory interface to the array.
 60. The system of claim 55, wherein one of the functions is providing a mixed serial and parallel memory interface to the array.
 61. The system of claim 55, wherein one of the functions is providing a testing function.
 62. The system of claim 55, wherein one of the functions is providing access to internal signals of the memory system.
 63. The system of claim 55, wherein at least one pin is coupled to the logic circuit through a TSV.
 64. The system of claim 55, wherein at least one pin is coupled to the logic circuit through a microbump.
 65. The system of claim 55, wherein at least one pin is coupled to the logic circuit through a bondwire.
 66. The system of claim 55, wherein the array is a SuperFlash array.
 67. The system of claim 55, wherein the standard pin is a serial SPI or SQI pin.
 68. The system of claim 55, wherein the standard pin is a parallel MPF pin.
 69. The system of claim 55, wherein the interface pin is deconfigured without ESD or with a smaller ESD structure.
 70. The system of claim 55, wherein the output pin is configured optimizing for 3D smaller load performance.
 71. The system of claim 55, wherein the input pin is configured optimizing for 3D performance.
 72. The system of claim 55 further comprising I/O data bandwidth that is more than the standard NOR memory I/O bandwidth.
 73. The system of claim 55 further comprising a microcontroller. 